Wenping Wang
ABSTRACT
Negative-bias-temperature-instability (NBTI) has become the primary limiting factor of circuit lifetime. In this work, we develop a general framework for analyzing the impact of NBTI on the performance of a circuit, based on various circuit parameters such as the supply voltage, temperature, and node switching activity of the signals etc. We propose an efficient method to predict the degradation of circuit performance based on circuit topology and the switching activity of the signals over long periods of time. We demonstrate our results on ISCAS benchmarks and a 65nm industrial design. The framework is used to provide key design insights for designing reliable circuits. The key design insights that we obtain are: (1) degradation due to NBTI is most sensitive on the input patterns and the duty cycle; the difference in the delay degradation can be up to 5X for various static and dynamic conditions, (2) during dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; (3) NBTI has marginal impact on the clock signal.
- M. A. Alam and S. Mahapatra. A comprehensive model of PMOS NBTI degradation. Microelectronics Reliability, 45:71--81, Aug. 2005.Google Scholar
Cross Ref
- S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula. Predictive modeling of the nbti effect for reliable design. IEEE Custom Integrated Circuits Conference, pages 189--192, Sep. 2006.Google ScholarCross Ref
- S. Borkar. Electronics beyond nano-scale CMOS. ACM/IEEE Design Automation Conference, pages 807--808, 2006. Google ScholarDigital Library
- S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan. A comprehensive framework for predictive modeling of negative bias temperature instability. IEEE International Reliability Physics Symposium, pages 273--282, 2004.Google ScholarCross Ref
- G. Chen, K. Y. Chuah, M. F. Li, D. S. Chan, C. H. Ang, J. Z. Zheng, Y. Jin, and D. L. Kwong. Dynamic NBTI of PMOS transistors and its impact on device lifetime. International Reliability Physics Symposium, pages 196--202, 2003.Google ScholarCross Ref
- N. K. et al. The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on mosfet scaling. VLSI Symp. On Tech., pages 73--74, 1999.Google Scholar
- http://www.cbl.ncsu.edu/.Google Scholar
- A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, and A. Varghese. Material dependence of hydrogen diffusion: Implication for nbti degradation. IEEE International Electron Devices Meeting, Dec. 2005.Google ScholarCross Ref
- S. V. Kumar, C. H. Kim, and S. S. Sapatnekar. An analytical model for negative bias temperature instability. International Conference on Comuter-Aided Design, pages 493--496, 2006. Google ScholarDigital Library
- B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electronic Device Letters, 26(8):560--562, Aug. 2005.Google ScholarCross Ref
- B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy. Temporal performance degradation under NBTI: Estimation and design for improved reliability of nanoscale circuits. ACM/IEEE Design, Automation, and Test Europe, pages 780--785, 2006. Google ScholarDigital Library
- J. Puchner and L. Hinh. NBTI reliability analysis for a 90nm CMOS technology. ESSDERC, pages 257--260, 2004.Google Scholar
- D. K. Schroder and J. A. Babcock. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. Journal of Applied Physics, 94(1):1--18, Jul. 2003.Google ScholarCross Ref
- R. Vattikonda, W. Wang, and Y. Cao. Modeling and minimization of pmos nbti effect for robust nanometer design. Design Automation Conference, pages 1047--1052, Jul. 2006. Google ScholarDigital Library
- W. Zhao and Y. Cao. New generation of predictive technology model for sub-45nm early design explorations. IEEE Tran. on Electron Devices, 53(11):2816--2823, Nov. 2006 (Available at http://www.eas.asu.edu/~ptm).Google ScholarCross Ref
Index Terms
- The impact of NBTI on the performance of combinational and sequential circuits
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