Fa Wang
ABSTRACT
Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Bayesian Model Fusion (BMF). Our key idea is to borrow the simulation data generated from an early stage (e.g., schematic level) to facilitate efficient high-dimensional performance modeling at a late stage (e.g., post layout) with low computational cost. Such a goal is achieved by statistically modeling the performance correlation between early and late stages through Bayesian inference. Several circuit examples designed in a commercial 32nm CMOS process demonstrate that BMF achieves up to 9x runtime speedup over the traditional modeling technique without surrendering any accuracy.
- Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2011.Google Scholar
- X. Li, J. Le and L. Pileggi, Statistical Performance Modeling and Optimization, Now Publishers, 2007. Google ScholarDigital Library
- Z. Feng and P. Li, "Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression," IEEE ICCAD, pp. 868--875, 2006. Google ScholarDigital Library
- A. Singhee and R. Rutenbar, "Beyond low-order statistical response surfaces: latent variable regression for efficient, highly nonlinear fitting," IEEE DAC, pp. 256--261, 2007. Google ScholarDigital Library
- A. Mitev, M. Marefat, D. Ma and J. Wang, "Principle Hessian direction based parameter reduction for interconnect networks with process variation," IEEE ICCAD, pp. 632--637, 2007. Google ScholarDigital Library
- T. McConaghy and G. Gielen, "Template-free symbolic performance modeling of analog circuits via canonical-form functions and genetic programming," IEEE Trans. on CAD, vol. 28, no. 8, pp. 1162--1175, Aug. 2009. Google ScholarDigital Library
- T. McConaghy, "High-dimensional statistical modeling and analysis of custom integrated circuits," IEEE CICC, 2011.Google Scholar
- X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling of analog/RF circuits," IEEE Trans. on CAD, vol. 29, no. 11, pp. 1661--1668, Nov. 2010. Google ScholarDigital Library
- X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, "Asymptotic probability extraction for nonnormal performance distributions," IEEE Trans. on CAD, vol. 26, no. 1, pp. 16--37, Jan. 2007. Google ScholarDigital Library
- M. Sengupta, S. Saxena, L. Daldoss, G. Kramer, S. Minehane and J. Cheng, "Application-specific worst case corners using response surfaces and statistical models," IEEE Trans. on CAD, vol. 24, no. 9, pp. 1372--1380, 2005. Google ScholarDigital Library
- Z. Wang and S. Director, "An efficient yield optimization method using a two step linear approximation of circuit performance," IEEE EDAC, pp. 567--571, 1994.Google Scholar
- A. Dharchoudhury and S. Kang, "Worse-case analysis and optimization of VLSI circuit performance," IEEE Trans. on CAD, vol. 14, no. 4, pp. 481--492, Apr. 1995. Google ScholarDigital Library
- G. Debyser and G. Gielen, "Efficient analog circuit synthesis with simultaneous yield and robustness optimization," IEEE ICCAD, pp. 308--311, 1998. Google ScholarDigital Library
- F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. Graeb and K. Antreich, "Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search," IEEE DAC, pp. 858--863, 2001. Google ScholarDigital Library
- X. Li, P. Gopalakrishnan, Y. Xu and L. Pileggi, "Robust analog/RF circuit design with projection-based performance modeling," IEEE Trans. on CAD, vol. 26, no. 1, pp. 2--15, Jan. 2007. Google ScholarDigital Library
- X. Li, W. Zhang, F. Wang, S. Sun and C. Gu, "Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion," IEEE ICCAD, 2012. Google ScholarDigital Library
- S. Ji, Y. Xue, and L. Carin, "Bayesian compressive sensing," IEEE Trans. on Signal Processing, pp. 2346--2356, Jun. 2008. Google ScholarDigital Library
- R. Myers and D. Montgomery, Response Surface Methodology: Process and Product Optimization Using Designed Experiments, Wiley-Interscience, 2002. Google ScholarDigital Library
- C. Bishop, Pattern Recognition and Machine Learning, Springer, 2006. Google ScholarDigital Library
Index Terms
- Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data
Recommendations
Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
Efficient performance modeling of today’s analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling ...
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information
ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided DesignEfficient performance modeling of today's analog and mixed-signal (AMS) circuits is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Co-Learning Bayesian Model Fusion (CL-BMF). ...
Correlated Bayesian Model Fusion: efficient performance modeling of large-scale tunable analog/RF integrated circuits
DAC '16: Proceedings of the 53rd Annual Design Automation ConferenceTunable circuit has emerged as a promising methodology to address the grand challenge posed by process variations. Efficient high-dimensional performance modeling of tunable analog/RF circuits is an important yet challenging task. In this paper, we ...
Comments