Paolo Mantovani
Emilio G. Cota
ABSTRACT
Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with loosely-coupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity.
- Andersen, T. M., et al. A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. In ISSCC Digest of Technical Papers (Feb. 2015), pp. 22--26.Google Scholar
Cross Ref
- Angiolini, F., et al. Contrasting a NoC and a traditional interconnect fabric with layout awareness. In DATE (Mar. 2006), pp. 124--129. Google ScholarDigital Library
- Arvind. Simulation is passé all future systems require FPGA prototyping. Keynote Address at Embedded System Week (ESWEEK) (Oct. 2014).Google Scholar
- Barker, K., et al. PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual, December 2013. http://hpc.pnnl.gov/projects/PERFECT/.Google Scholar
- Bhattacharjee, A., et al. Full-system chip multiprocessor power evaluations using fpga-based emulation. In ISLPED (Aug 2008), pp. 335--340. Google ScholarDigital Library
- Bogdan, P., et al. An optimal control approach to power management for multi-voltage and frequency islands multiprocessor platforms under highly variable workloads. In NOCS (May 2012), pp. 35--42. Google ScholarDigital Library
- Borkar, S., et al. The future of microprocessors. Communication of the ACM 54 (May 2011), 67--77. Google ScholarDigital Library
- Burton, E. A., et al. FIVR -- fully integrated voltage regulators on 4th generation Intel Core SoCs. In APEC (Mar. 2014), pp. 16--20.Google Scholar
- Carloni, L. P. From latency-insensitive design to communication-based system-level design. Proceedings of the IEEE 103, 11 (Nov. 2015), 2133--2151.Google ScholarCross Ref
- Chang, L., et al. A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2. In VLSI symp. (June 2010), pp. 55--56.Google Scholar
- Cota, E., et al. An analysis of accelerator coupling in heterogeneous architectures. In DAC (June 2015), pp. 1--6. Google ScholarDigital Library
- Dally, W. J., et al. Route packets, not wires: on-chip interconnection networks. In DAC (June 2001), pp. 684--689. Google ScholarDigital Library
- Dasika, G., et al. DVFS in loop accelerators using BLADES. In DAC (June 2008), pp. 894--897. Google ScholarDigital Library
- DiBene, J. T., et al. A 400A fully integrated silicon voltage regulator with in-die magnetically coupled embedded inductors. In APEC (Feb. 2010).Google Scholar
- Esmaeilzadeh, H., et al. Dark silicon and the end of multicore scaling. In ISCA (June 2011), pp. 365--376. Google ScholarDigital Library
- Herbert, S., et al. Exploiting process variability in voltage/frequency control. IEEE Trans. VLSI Systems 20, 8 (Aug. 2012), 1392--1404. Google ScholarDigital Library
- Horowitz, M. Computing's energy problem (and what we can do about it). In ISSCC Digest of Technical Papers (Feb. 2014), pp. 10--14.Google Scholar
- Jevtic, R., et al. Per-core DVFS with switched-capacitor converters for energy efficiency in manycore processors. IEEE Trans. on VLSI Systems 23, 4 (Apr. 2015), 723--730.Google ScholarDigital Library
- Karnik, T., et al. Power management and delivery for high-performance microprocessors. In DAC (June 2013), pp. 1--3. Google ScholarDigital Library
- Kaxiras, S., et al. Computer Architecture Techniques for Power-Efficiency, 1st ed. Morgan and Claypool Publishers, 2008. Google ScholarDigital Library
- Kim, W., et al. System level analysis of fast, per-core DVFS using on-chip switching regulators. In HPCA (Feb. 2008), pp. 123--134.Google Scholar
- Kornaros, G., et al. Dynamic power and thermal management of noc-based heterogeneous mpsocs. ACM Trans.s on Reconfigurable Technology and Systems 7, 1 (Feb. 2014), 1--26. Google ScholarDigital Library
- Mantovani, P., Guglielmo, G. D., and Carloni, L. P. High-level synthesis of accelerators in embedded scalable platforms. In ASP-DAC (Jan. 2016), pp. 204--211.Google ScholarDigital Library
- Park, J., et al. Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors. In ISLPED (Aug. 2010), pp. 419--424. Google ScholarDigital Library
- Rangan, K. K., et al. Thread motion: Fine-grained power management for multi-core systems. In ISCA (June 2009), pp. 302--313. Google ScholarDigital Library
- Rusu, S., et al. A 22 nm 15-Core Enterprise Xeon Processor Family. IEEE Journal of Solid-State Circuits 50, 1 (Jan. 2015), 35--48.Google ScholarCross Ref
- Salihundam, P., et al. A 2 Tb/s 6x4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. IEEE Journal of Solid-State Circuits 46, 4 (Apr. 2011), 757--766.Google ScholarCross Ref
- Semeraro, G., et al. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In HPCA (2002), pp. 29--40. Google ScholarDigital Library
- Simunic, T., et al. Dynamic voltage scaling and power management for portable systems. In DAC (2001), pp. 524--529. Google ScholarDigital Library
- Strano, A., et al. A library of dual-clock FIFOs for cost-effective and flexible MPSoC design. In SAMOS (July 2010), pp. 20--27.Google ScholarCross Ref
- Sturcken, N., et al. A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer. IEEE Journal of Solid-State Circuits 48, 1 (Jan. 2013), 244--254.Google ScholarCross Ref
- Taylor, M. B. Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In DAC (June 2012), pp. 1131--1136. Google ScholarDigital Library
- Tien, K., et al. An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors. In VLSI symp. (June 2015), pp. 16--19.Google Scholar
- Venkatesh, G., et al. Conservation cores: reducing the energy of mature computations. In ASPLOS (Mar. 2010), pp. 205--218. Google ScholarDigital Library
- Wang, N., et al. Ultra-high-Q air-core slab inductors for on-chip power conversion. In IEDM (Dec. 2014), pp. 15--17.Google ScholarCross Ref
- Wang, X., et al. Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors. In DATE (Mar. 2014), pp. 1--4. Google ScholarDigital Library
- White, M. A. Low power is everywhere. Synopsys Insight Newsletter (online), 2012.Google Scholar
Recommendations
Fine-grained DVFS using on-chip regulators
Limit studies on Dynamic Voltage and Frequency Scaling (DVFS) provide apparently contradictory conclusions. On the one hand early limit studies report that DVFS is effective at large timescales (on the order of million(s) of cycles) with large scaling ...
FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications
ISVLSI '10: Proceedings of the 2010 IEEE Annual Symposium on VLSIEmbedded high performance computing applications, like for example image processing in surveillance systems, are very compute intensive due to the complexity of the algorithms. Additionally to the computing intensive data processing, the power ...
Fine-Grained Interconnect Synthesis
Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015One of the key challenges for the FPGA industry going forward is to make the task of designing hardware easier. A significant portion of that design task is the creation of the interconnect pathways between functional structures. We present a synthesis ...
Comments