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Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores

Published:05 June 2016Publication History

ABSTRACT

In heterogeneous MPSoCs, memory interference between the CPU and realtime cores is a critical impediment to system performance. Previous memory schedulers adopt the classic two-tier queuing system, but unfortunately the use of two-tier queuing deteriorates the QoS of scheduling policies. In this paper, we propose the Single-Tier Virtual Queuing (STVQ) memory controller for efficacious QoS-aware scheduling. The STVQ memory controller maintains single-tier transaction queues and employs separable allocation for transaction scheduling with high scalability. A multi-source realtime scheduling algorithm is further presented. The STVQ controller achieves up to 13.9% less CPU IPC slowdown than previous schedulers with no frame rate penalty on realtime cores.

References

  1. J. Power, A. Basu, J. Gu, S. Puthoor, B. M. Beckmann, M. D. Hill, S. K. Reinhardt, and D. A. Wood. Heterogeneous system coherence for integrated CPU-GPU systems. In ACM/IEEE MICRO, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. R. Ausavarungnirun, K. Chang, L. Subramanian, G. H. Loh, and O. Mutlu. Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. In ACM ISCA, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. M. K. Jeong, M. Erez, C. Sudanthi, and N. Paver. A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC. In ACM/IEEE DAC, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. J. Lee, S. Li, H. Kim, and S. Yalamanchili. Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture. J. Parallel Distrib. Comput., 73(12):1525--1538, Dec. 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. A. K. Mishra, O. Mutlu, and C. R. Das. A heterogeneous multiple network-on-chip design: An application-aware approach. In ACM/IEEE DAC, 2013. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In ACM ISCA, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. In IEEE HPCA, 2010.Google ScholarGoogle Scholar
  8. Y. Kim, M. Papamichael, O. Mutlu, and M. Harchol-Balter. Thread cluster memory scheduling: Exploiting differences in memory access behavior. In ACM/IEEE MICRO, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. J. Cazorla. A dual-criticality memory controller (DCmc): Proposal and evaluation of a space case study. In IEEE RTSS, 2014.Google ScholarGoogle ScholarCross RefCross Ref
  10. D. U. Becker and W. J. Dally. Allocator implementations for network-on-chip routers. In ACM/IEEE SC, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. B. Jacob, S. Ng, and D. Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. DRAMSim: A memory-system simulator. In SIGARCH Computer Architecture News, 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Gallium3D. http://en.wikipedia.org/wiki/Gallium3D/.Google ScholarGoogle Scholar

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  • Published in

    cover image ACM Other conferences
    DAC '16: Proceedings of the 53rd Annual Design Automation Conference
    June 2016
    1048 pages
    ISBN:9781450342360
    DOI:10.1145/2897937

    Copyright © 2016 ACM

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 5 June 2016

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