Doowon Lee
Avi Ziv
ABSTRACT
Post-silicon validation has become essential in catching hard-to-detect, rarely-occurring bugs that have slipped through pre-silicon verification. Post-silicon validation flows, however, are challenged by limited signal observability, which impacts their ability of diagnosing and detecting bugs. Indeed, bug manifestations during the execution of constrained-random tests may be masked and be unobservable from the test's outputs. The ability to evaluate the bug-masking rate of a test provides great value in generating and/or selecting effective tests for high coverage regressions.
To this end, we propose an efficient, static bug-masking analysis solution, called BugMAPI. BugMAPI tracks the information flow in a test program, and it estimates the probability that bugs go undetected by the checking mechanisms in place in the post-silicon platform. To achieve this goal, we leverage static code analysis and a novel, lightweight, probability estimation algorithm. We evaluated BugMAPI on a range of industrial constrained-random tests and a range of bug injection models, and we found that it can estimate bug-masking rates with an accuracy of 77% in 3 orders-of-magnitude less time, compared to an ideal dynamic analysis solution.
- A. Adir et al. Threadmill: a post-silicon exerciser for multi-threaded processors. In Proc. DAC, 2011. Google Scholar
Digital Library
- N. Binkert et al. The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2), 2011. Google ScholarDigital Library
- D. Denning and P. Denning. Certification of programs for secure information flow. Communications of the ACM, 20(7), 1977. Google ScholarDigital Library
- F. Fallah, S. Devadas, and K. Keutzer. OCCOM---efficient computation of observability-based code coverage metrics for functional verification. IEEE Trans. CAD, 20(8), 2001. Google ScholarDigital Library
- S. Feng et al. Shoestring: probabilistic soft error reliability on the cheap. In Proc. ASPLOS, 2010. Google ScholarDigital Library
- H. Foster. Trends in functional verification: a 2014 industry study. In Proc. DAC, 2015. Google ScholarDigital Library
- N. Foutris et al. Accelerating microprocessor silicon validation by exposing ISA diversity. In Proc. MICRO, 2011. Google ScholarDigital Library
- IBM. Power ISA Version 2.07B, 2015.Google Scholar
- D. Lin et al. Effective post-silicon validation of system-on-chips using quick error detection. IEEE Trans. CAD, 33(10), 2014.Google ScholarCross Ref
- P. Mishra and N. Dutt. Graph-based functional test program generation for pipelined processors. In Proc. DATE, 2004. Google ScholarDigital Library
- A. Nahir et al. Post-silicon validation of the IBM POWER8 processor. In Proc. DAC, 2014. Google ScholarDigital Library
- J. Newsome and D. Song. Dynamic taint analysis for automatic detection, analysis, and signature generation of exploits on commodity software. In Proc. NDSS, 2005.Google Scholar
- M. Rinard. Analysis of multithreaded programs. In Static Analysis, Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2001. Google ScholarDigital Library
- A. Sabelfeld and A. Myers. Language-based information-flow security. Selected Areas in Communications, IEEE Journal on, 21(1), 2003. Google ScholarDigital Library
- S. Thiruvathodi and D. Yeggina. A random instruction sequence generator for ARM based systems. In Proc. MTV, 2014. Google ScholarDigital Library
- I. Wagner and V. Bertacco. Reversi: post-silicon validation system for modern microprocessors. In Proc. ICCD, 2008.Google ScholarCross Ref
Index Terms
- Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification
Recommendations
Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)
Instruction Footprint Recording and Analysis (IFRA) overcomes challenges associated with an expensive step in post-silicon validation of processors--pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-...
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs
Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex multi and many-core SoCs. However, there is little data evaluating the coverage of post-silicon validation efforts on ...
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
DAC '11: Proceedings of the 48th Design Automation ConferenceThe growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification ...
Comments